Sample-and-hold (S&H) circuits are used to sample an input signal and store that sample for a predetermined time period. These circuits are widely used in signal processing applications. During the sample mode of operation, the output of the S&H is a replica of the input signal. During the hold mode, the output retains the value of the input signal at the instant the S&H enters the hold mode from the sample mode. The better the S&H, the more accurate the held value is to the input value at that instant. However, switching transients by the internal circuitry of the S&H introduce an error in the resulting held value, referred to as a pedestal error or hold step. Further, the better the S&H, the lower the drift (droop rate) of the held value with time.
S&H circuits have three basic components: an input amplifier, an integrator or storing means, and a coupling means which selectively couples the input amplifier to the integrator during the sample mode and decouples the integrator from the amplifier during the hold mode. Some designs employ a conventional operational amplifier as the input amplifier with a series of diodes or transistors adapted to form the coupling means. The integrator is usually a suitably adapted capacitor. The operational amplifier as an input amplifier has the disadvantage of low impedance output so that the coupling means (diodes or transistors) must have a low impedance during the sample mode and a high impedance (with very low leakage) during the hold mode. A second approach integrates the input amplifier and the coupling means by using an operational transconductance amplifier (OTA) as the input amplifier. The OTA is additionally responsive to the output signal from the integrator for negative feedback. The OTA has a very high output impedance such that a separate coupling means is not needed. Current is sourced (or sinked) by the OTA during the sample mode (the OTA is active) to force the charge in the capacitor integrator and, hence, the output signal to follow the input signal. However, the OTA, as known in the prior art, has significant leakage current when disabled (the OTA is in stand-by) during the hold mode, thereby increasing the drift rate of the S&H. Further, as the S&H transitions from the sample to the hold mode, the OTA introduces significant extraneous transient current spikes into the integrator, generating the pedestal error.